The present invention pertains to the field of computer architecture, and more particularly, this invention relates to an apparatus and a method for interfacing a non-sequential 486 interface burst interface to a sequential ASB interface.
A prior computer system typically includes a central processing unit (CPU), a system bus, memory and peripheral devices. The CPU is connected with the bus so as to communicate with the memory and peripheral devices. In one instance, the memory includes random access memory (RAM) and read-only memory (ROM). Typical peripheral devices include a keyboard, a mouse, a display, a hard disk drive, a serial communication port, a parallel communication port, and a network connection. The ability of the CPU to communicate with various devices coupled with the system bus is realized by maintaining interface compatibility between the CPU and various peripheral devices via the system bus. However, certain applications require the use of cost effective processors that might not be compatible with modern system buses and memory systems.
One prior approach to maintaining compatibility between a CPU and peripheral components is to use a CPU and peripheral devices that both support sequential burst order read operations. However, older CPUs such as the Intel 486(trademark)DX processor use an Intel burst order wherein the read burst order from the processor is sequential for some read operations and is non-sequential for other read operations. When there is a need to combine such a processor with a modern standard bus, such as an ASB bus, there exists a problem in that the ASB bus cannot support non-sequential burst access methods.
Another prior approach to maintaining compatibility between a CPU and peripheral components is to use a CPU and peripheral devices that both support non-sequential burst order read operations. However, as discussed above, modern standard buses, such as an ASB bus, cannot support non-sequential burst access methods.
The present invention relates to a method and apparatus for interfacing older cost effective processors with modern buses and memory systems. In one embodiment, an Intel 486(trademark)DX processor is interfaced to a memory subsystem through a standard bus, such as an ASB bus. The ASB bus cannot support a non-sequential burst access method, whereas the 486(trademark)DX processor uses an Intel read burst order that is sequential for some read operations and non-sequential for other read operations. Other older processors pose similar problems in that some read operations are sequential and others are non-sequential.
According to one aspect of the invention, an apparatus is provided for interfacing a processor with a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential. The apparatus includes an interface adaptor circuit that is coupled between the processor and the bus. The interface adaptor circuit is operative as a burst order translator between the processor and the bus, and has a bridge configured to connect together the processor and the bus. The bridge is operative to translate processor burst operations into operations supported by the bus. The bridge has a processor interface coupled between the processor and the interface adaptor circuit and a bus interface coupled between the bus and the interface adaptor circuit. The bridge is operative to enable compatibility between the processor interface and the bus interface such that non-sequential burst access from the processor is supported and deliverable as sequential burst access to the bus.
According to another aspect of the invention, a computer system is provided having a processor, a bus and an interface adaptor circuit. The processor is configured to perform burst read operations in both a sequential and a non-sequential manner. The bus is incapable of supporting burst read operations that are non-sequential. Furthermore, the interface adaptor circuit is coupled between the processor and the bus, and has a bridge configured to connect together the processor and the bus. The bridge is operative to translate processor burst operations into bus-compatible burst operations. Additionally, the bridge is configured to enable compatibility between the processor and the bus such that non-sequential burst access from the processor is supported and deliverable as sequential burst access to the bus.
According to yet another aspect of the invention, a method is provided for communicating between a processor and a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential. The method includes the steps of: configuring an interface adaptor circuit between the processor and the bus to operate as a burst order translator; receiving burst read operations from the processor comprising at least one of sequential and non-sequential read operation burst orders; and translating the received processor burst operations into operations supported by the bus so as to enable compatibility between the processor and the bus such that non-sequential burst access from the processor is supported and deliverable as sequential burst access to the bus.